Applicant hereby incorporates by reference Japanese Application No. 2001-003959, filed Jan. 11, 2001, in its entirety.
1. Technical Field
The present invention relates to semiconductor devices including a non-volatile memory transistor and methods for manufacturing the same.
2. Related Art
A transistor having a split-gate structure is known as one of the devices that are applied to an electrically erasable programmable ROM (EEPROM). FIG. 7 schematically shows a cross-sectional view of one example of a conventional semiconductor device including a non-volatile memory transistor. The semiconductor device includes a non-volatile memory transistor having a split-gate structure (hereafter referred to as a xe2x80x9cmemory transistorxe2x80x9d) 300.
The memory transistor 300 has, in the case of an n-type transistor as an example, a source region 14 and a drain region 16 composed of n+-type impurity diffusion layers formed in a silicon substrate 10 of P-type, and a first insulation layer 70 as a gate dielectric layer formed on a surface of the silicon substrate 10. A floating gate 72, a third insulation layer 76 and a control gate 78 are successively formed on the first insulation layer 70.
A second insulation layer 74 is formed on the floating gate 72. The second insulation layer 74 is composed of an insulation layer that is formed by selectively oxidizing a part of a polysilicon layer that becomes to be the floating gate 72. In other words, the second insulation layer 72 has a structure in which the film thickness thereof becomes thinner from its center toward its end sections, as shown in FIG. 7. As a result, upper edge sections 720 of the floating gate 72 form sharp edges, such that an electric field concentration is apt to occur at the upper edge sections 720.
For operating the memory transistor with a split-gate structure 300, a channel current is flown between the source region 14 and the drain region 16 to thereby inject a charge (hot electrons) in the floating gate 72 as indicated by an arrow A10 when data is written. When data is erased, a predetermined high voltage is applied to the control gate 78 to thereby transfer the charge stored in the floating gate 72 through the third insulation layer 76 to the control gate 78 as indicated by an arrow B10 by Fowler-Nordheim tunneling conduction (FN conduction).
Certain embodiments relate to a method for manufacturing a semiconductor device including a non-volatile memory transistor, the method including the steps of: (a) forming a first insulation layer that functions as a gate dielectric layer on a semiconductor layer; (b) forming a floating gate having a specified pattern on the first insulation layer; (c) forming a second insulation layer that contacts at least a part of the floating gate and functions as a tunnel dielectric layer; (d) forming a control gate having a specified pattern over the second insulation layer; (e) forming an impurity diffusion layer that forms source and drain regions in the semiconductor layer; (f) depositing an additional insulation layer on the semiconductor layer including the control gate and the floating gate; and (g) etching the additional insulation layer to form at least a first sidewall insulation layer on a side of the floating gate and a second sidewall insulation layer on a side of the control gate over the floating gate, wherein the step (g) is conducted such that a portion of the additional insulation layer remains between the first sidewall insulation layer and the second sidewall insulation layer above the floating gate, and the floating gate is not exposed.
Embodiments also relate to a method for manufacturing a semiconductor device having a non-volatile memory transistor including a MIS transistor, a floating gate and a control gate, the method for manufacturing a semiconductor device including the steps of: (a) forming a floating gate over a semiconductor layer; (b) forming a first insulation layer that functions as at least a part of a tunnel insulation layer of the non-volatile memory transistor; (c) forming a control gate over a portion above the floating gate toward a portion above the semiconductor layer; (d) forming a second insulation layer above the semiconductor layer including the non-volatile memory transistor and the MIS transistor; and (e) forming a side wall at least at the MIS transistor by conducting an etching step on the second insulation layer, wherein the etching step in the step (e) is conducted such that at least the floating gate is not exposed.
Embodiments also relate to a semiconductor device having a non-volatile memory transistor, the semiconductor device including a semiconductor layer and a floating gate disposed over the semiconductor layer through a first insulation layer as a gate dielectric layer. The device also includes a second insulation layer that contacts at least a part of the floating gate and functions as a tunnel dielectric layer. A control gate is formed over the second insulation layer. An impurity diffusion layer is formed in the semiconductor layer, which forms source and drain regions. A first sidewall insulation layer is formed on a side of the floating gate. A second sidewall insulation layer is formed on a side of the control gate above the floating gate. A third insulation layer is formed between the first sidewall insulation layer and the second sidewall insulation layer and above the floating gate, the third insulation layer being continuous to the first sidewall insulation layer and the second sidewall insulation layer.
Embodiments also relate to a method for manufacturing a semiconductor device including a non-volatile memory transistor, the method including forming a gate dielectric layer on a semiconductor layer and forming a floating gate on the gate dielectric layer. The method also includes forming an insulating layer that contacts at least a part of the floating gate, wherein at least a portion of the insulating layer acts as a tunnel dielectric layer. The method also includes forming a control gate over a portion of the insulating layer. Source and drain regions are formed in the semiconductor layer. The method also includes forming a sidewall insulating region that cover a side surface of the control gate over the floating gate and extends continuously from the side surface of the control gate to a position on a side of the floating gate.
Embodiments also relate to a semiconductor device having a non-volatile memory transistor, the semiconductor device including a semiconductor layer, a gate dielectric layer, and a floating gate disposed over the semiconductor layer and gate dielectric layer. The devise also includes an insulation layer that contacts at least a part of the floating gate and is capable of acting as a tunnel dielectric layer. The device also includes a control gate formed over at least a portion of the insulation layer, and source and drain regions in the semiconductor layer. The device also includes a sidewall insulation region extending continuously from a position on a side surface of the control gate above the floating gate to a position at a side of the floating gate.